Careers – Zhejiang Zentel Memory

Recruitment

Back-end design engineer

Recruiting Department：R&D Department

Number of recruits：5

Release date：2022-08-26

Responsibilities：

1. Full design flow from netlist to chip tape-out;
2. Automatic P&R, clock tree synthesis, static timing analysis, power consumption calculation, IR drop analysis, crosstalk analysis, physical verification (DRC/LVS), etc.
3. Provide chip area and power consumption estimation based on chip architecture;
4. Back-end design and delivery;
5. Work together with foundry and IP suppliers for tape-out related work;

Job Requirements：

1. Master degree or above, major in electronic engineering, microelectronics or other related fields, more than 5 years experience in digital back-end design, the degree requirement can be relaxed for excellent students;
2. Familiar with digital IC design flow;
3. Familiar with EDA tools such as Synopsys/Cadence/Mentor (such as Design Compiler, ICC, PrimeTime, Virtuoso, etc.);
4. Proficient in scripting language Perl, TCL and other similar languages;
5. Self-driven, team player, good communication skills.

Digital IC design engineer

Recruiting Department：R&D Department

Number of recruits：5

Release date：2022-08-26

Responsibilities：

1. Digital IC design and verification;
2. RTL writing, simulation verification, synthesis, timing analysis and testability design;
3. Coordinate with back-end engineers to complete the layout;
4. Digital front-end design and project management, including RTL design, RTL verification, formal verification, RTL synthesis, timing verification, etc., To successfully achieve chip functions and performance;
5. Proficient in using EDA tools for digital IC design, including simulation, synthesis, timing analysis, etc.;
6. Able to guide the design under different test schemes, and assist in chip samples;
7. Prepare relevant technical documents.

Job Requirements：

1. Familiar with digital IC design flow, more than 5 years working experience is preferred;
2. Proficient in RTL coding, logic synthesis, static timing analysis, back-end physical implementation and formal verification, etc.;
3.Familiar with EDA tools such as VCS, NC-Verilog, Vivado, DC, PT and Formality;
4. DDR, USB, MIPI design experience is preferred;
5. Experience in tapeout is preferred;
6. Strong initiative, sense of responsibility, work carefully, good team spirit.

Contact HR

E-mail：hrzp@zentel.com

Telephone：0571-28882030

Interested parties please send your resume to hr or call

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