Careers – Zhejiang Zentel Memory

AE Engineer

Recruiting Department：Product Engineering Department | Hangzhou | Bachelor/master

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Number of recruits：2

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Release date：2024-09-29

Responsibilities：

1. 1. System performance test and verification: Develop and implement various test platforms, conduct DRAM performance testing and analysis, analyze test data, identify performance bottlenecks, cooperate with product engineering and R&D teams, and verify functions.
2. Troubleshooting and debugging: Monitor system operation status, respond and solve problems quickly, work with customer hardware and software teams to locate and repair defects.
3. Document and report writing: Write technical documentation, including design specifications, test plans and reports, training materials and instruction manuals to provide technical support.
4. Customer Support: Provide technical advice to customers, solve problems in use, collect customer feedback, and convert it into improvement suggestions.
5. Market research and technical update: Keep an eye on industry trends and new technologies, analyze competitors' products, attend industry conferences and seminars to share experience and knowledge.

Job Qualifications:：

1. Bachelor's degree in computer science, communication engineering, electronic information engineering, or automation-related engineering; A master's degree is preferred.
2. Basic DRAM architecture and its working principle/high-speed circuit design /PCB circuit layout and design specifications/Microwave circuit or signal integrity and power integrity analysis/microprocessor system/embedded system, master at least one of the above knowledge.
3. Master at least one programming language (such as C/C++, Python), be able to write tests or auxiliary tools.
4. Experience in design and execution of test plan, familiar with oscilloscope or logic analyzer. Be able to use data analysis tools (such as MATLAB, Excel) for performance analysis and troubleshooting.
5. Experience in DRAM or related product design and use, participation in related course content and competition experience is preferred.
6. Able to read technical documents and communicate in English.

Layout engineer

Recruiting Department：R&D | Hangzhou | Bachelor/master

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Number of recruits：2

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Release date：2024-09-29

Responsibilities：

1. Layout design of analog and mixed-signal circuits using Cadence Virtuoso.
2. Perform design rule checks (DRC), Electrical Rule checks (ERC), and Layout and Schematic Comparison (LVS).
3. Work closely with the front-end design team to ensure layout design meets circuit design requirements.
4. Optimize layout to improve chip performance and yield.
5. Write detailed layout design documents and technical reports.
6. Participate in project management and team work to ensure project delivery on time.

Job Qualifications:：

1. Bachelor degree or above in electronic engineering, microelectronics or related field.
2. Proficient in layout design using Cadence Virtuoso.
3. Good English communication skills, CET-6 is preferred.
4. Familiar with IC design process and design rules.
5. Experience with APR (Automatic layout and wiring) is preferred.
6. Familiarity with SKILL or other programming languages is a plus.
7. Ability to write DRC/LVS rules is a plus
8. Good team player and communication skills.

Analog circuit design

Recruiting Department：R&D | Hangzhou/Beijing | master/PhD

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Number of recruits：5

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Release date：2022-08-26

Responsibilities：

1. Responsible for the design and verification of analog circuits, including: bandgap reference, operational amplifier, high-speed I/O interface, ADC, LDO, PUMP and other modules;
2. Responsible for the writing of related design documents; Assist layout engineer to complete floor plan, and check key layout;
3. Assisted the Marketing Department to complete the initial definition, analysis and planning of the project; Assist system engineer to develop chip SPEC, and carry out IC test and verification;
4. assist application engineers, field application engineers to solve customer and other application problems.

Job Qualifications:：

1. Master degree or above, electronics, microelectronics, integrated circuit and other related majors.
2. Familiar with analog circuit direction module design, band-gap benchmark, operational amplifier, LDO, ADC, PUMP module experience is preferred.
3. Familiar with hspice, spectre and other design simulation tools.
4. With project circuit forward design experience is preferred.
5. Have the ability to layout floor plan.
6. Have knowledge and understanding of semiconductor devices and process flow.
7. Persistent learning attitude towards analog circuit design.
8. Good English communication skills, CET-6 is preferred.
9. Good team work spirit and communication skills.

Digital IC design engineer

Recruiting Department：R&D Department

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Number of recruits：5

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Release date：2022-08-26

Responsibilities：

1. Digital IC design and verification;
2. RTL writing, simulation verification, synthesis, timing analysis and testability design;
3. Coordinate with back-end engineers to complete the layout;
4. Digital front-end design and project management, including RTL design, RTL verification, formal verification, RTL synthesis, timing verification, etc., To successfully achieve chip functions and performance;
5. Proficient in using EDA tools for digital IC design, including simulation, synthesis, timing analysis, etc.;
6. Able to guide the design under different test schemes, and assist in chip samples;
7. Prepare relevant technical documents.

Job Requirements：

1. Familiar with digital IC design flow, more than 5 years working experience is preferred;
2. Proficient in RTL coding, logic synthesis, static timing analysis, back-end physical implementation and formal verification, etc.;
3.Familiar with EDA tools such as VCS, NC-Verilog, Vivado, DC, PT and Formality;
4. DDR, USB, MIPI design experience is preferred;
5. Experience in tapeout is preferred;
6. Strong initiative, sense of responsibility, work carefully, good team spirit.